Intel researchers see a path to one trillion transistor chips by 2030

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Intel has announced that its researchers are planning a way to make the chips 10 times denser through packaging improvements and a layer of a material just three atoms thick. And it could pave the way for a trillion transistors to be installed on a chip package by 2030.

Moore’s Law is supposed to be dead. Chips aren’t supposed to get better, at least not with advancements in traditional manufacturing. It’s a lamentable notion on the 75th anniversary of the invention of the transistor. In 1965, Intel Chairman Emeritus Gordon Moore predicted that the number of components, or transistors, on a chip would double every two years.

This law lasted for decades. Chips have become faster and more efficient. Chipmakers have reduced the dimensions of chips, and goodness has resulted. Electrons in a miniaturized chip had shorter distances to travel. Thus, the chip became faster. And the shorter distances meant the chip used less material, making it cheaper. And so the steady march of Moore’s Law meant that chips could get faster, cheaper and even more energy efficient at the same time.

But Moore’s Law really depended on brilliant human engineers coming up with better chip designs and continued miniaturization in manufacturing. In recent years, it has become more difficult to make this progress. The design of the chip clashed with the laws of physics. With atomic layers a few atoms thick, it was no longer possible to shrink. And so Nvidia CEO Jensen Huang recently said, “Moore’s Law is dead.


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Intel showed how it could build chips with complex interconnected packages.

Now is not the right time, since we are about to start building the metaverse. Moore’s Law is key to meeting the world’s insatiable computing needs, as rising data consumption and the trend towards increased artificial intelligence (AI) are driving the greatest acceleration in demand ever.

A week after Nvidia CEO said this, Intel CEO Pat Gelsinger said Moore’s Law is alive and well. This is not a surprise since he has bet tens of billions of dollars on new chip factories in the United States. However, his researchers support him at the International Electron Devices Meeting. Intel has made it clear that these advances may not exist for another five to ten years.

In papers at the research event, Intel outlined breakthroughs to keep Moore’s Law on track to reach one trillion transistors in one package over the next decade. At IEDM, Intel researchers are showcasing advances in 3D packaging technology with a new 10-fold improvement in density, said Paul Fischer, Director and Principal Component Research Engineer at Intel, during a press briefing.

“Our mission is to keep our process technology options rich and comprehensive,” he said.

These packages have been used in innovative ways lately; Intel’s rival Advanced Micro Devices has announced that its latest graphics chip has one processor chip and six memory chips, all wired together in a single package. Intel said it collaborates with government entities, universities, industry researchers and chip equipment companies. Intel shares the fruits of research at places like the IEDM event.

Intel also unveiled new materials for scaling 2D transistors beyond RibbonFET, including ultra-thin materials just three atoms thick. He also described new possibilities in power and memory efficiency for higher performance computing; and advances in quantum computing.

“Seventy-five years after the invention of the transistor, the innovation behind Moore’s Law continues to meet the exponentially growing global demand for computing,” said Gary Patton, Intel vice president for component research and design, in a statement. “At MEI 2022, Intel is showcasing both the groundbreaking and real-world research advancements needed to overcome current and future barriers, meet this insatiable demand, and keep Moore’s Law alive for years to come. .

75 years of the transistor

Layers between on-chip circuits can be as small as three atoms thick.

To commemorate the 75th anniversary of the transistor, Ann Kelleher, Intel’s Executive Vice President and General Manager of Technology Development, will host a plenary session at the MEI. Kelleher will outline pathways for continued industry innovation – rallying the ecosystem around a systems-based strategy to meet the growing global demand for computing and innovate more effectively to advance at the pace of the law of Moore.

The session “Let’s celebrate 75 years of the transistor!” A Look at the Evolution of Moore’s Law Innovation,” takes place at 9:45 a.m. PST on December 5.

To make the necessary progress, Intel has a multi-pronged approach of “increasing importance and certainly growing influence within Intel” to examine multiple disciplines.
Intel needs to advance in chip materials, chip manufacturing equipment, design and packaging, Fischer said.

“3D packaging technology enables the seamless integration of chips,” or multiple chips in a package, he said. “We are blurring the line between the end of silicon and the beginning of packaging.”

Continuous innovation is the cornerstone of Moore’s Law. Over the past two decades, many of the key innovation milestones for continuous power, performance, and cost improvements—including strained silicon, Hi-K metal gate, and FinFET—in computers personal, GPUs and data centers started with Intel’s Component Research Group.

Other research, including RibbonFET gate-all-around (GAA) transistors, PowerVia back-feed technology, and packaging breakthroughs like EMIB and Foveros Direct, are on the roadmap today.

At IEDM 2022, Intel’s Component Research Group said it is developing new 3D hybrid bond packaging technology to enable seamless integration of chiplets; ultra-thin 2D materials to fit more
transistors on a single chip; and new possibilities in power and memory efficiency for higher performance computing.

How Intel will do it

Intel foresees a voracious demand for computing power.

Researchers have identified new materials and processes that blur the line between packaging and silicon. Intel said it plans to go from tens of billions of transistors on a chip today to a trillion transistors on a package, which can hold many chips.

One way forward is to use a package capable of achieving 10 times greater interconnect density, leading to near-monolithic chips. Intel’s hardware innovations have also identified practical design choices that can meet the demands of scaling transistors using a new material just three atoms thick, allowing the company to continue to scale. beyond the RibbonFET.

Intel’s latest Hybrid Link research presented at IEDM 2022 shows an additional 10x improvement in density for power and performance compared to Intel’s IEDM 2021 research presentation.

Continuous scaling of the hybrid link to three nanometer pitch allows for interconnect densities and bandwidths similar to those found on monolithic system-on-chip connections. A nanometer is one billionth of a meter.

Intel said it was looking for ultra-thin “2D” materials to fit more transistors on a single chip. Intel demonstrated an all-around-gate stacked nanosheet structure using a thin 2D channel just three atoms thick, while achieving near-ideal transistor switching on a dual-gate structure at room temperature with low leakage current .

These are two key breakthroughs needed to stack GAA transistors and go beyond the fundamental limits of silicon.

The researchers also revealed the first comprehensive analysis of electrical contact topologies to 2D materials that could pave the way for high-performance and scalable transistor channels.

To use chip area more efficiently, Intel is redefining scaling by developing memory that can be placed vertically above transistors. In an industry first, Intel is introducing stacked ferroelectric capacitors that match the performance of conventional ferroelectric trench capacitors and can be used to build FeRAM on a logic chip.

An industry-first device-level model captures mixed phases and faults for enhanced ferroelectric hafnia devices, marking significant progress for Intel in supporting industry tools to develop new new memories and ferroelectric transistors.

Intel sees a path to trillion-dollar transistor chips with several approaches.

By bringing the world closer to transitioning beyond 5G and solving energy efficiency challenges, Intel is building a viable path to 300 millimeter GaN-on-silicon wafers. Intel’s breakthroughs in this area demonstrate a 20x gain over industry-standard GaN and set an industry-record figure of merit for high-performance power delivery.

Intel is making inroads into super power-efficient technologies, especially transistors that don’t forget, retaining data even when power is removed. Already, Intel researchers have broken down two of the three barriers preventing the technology from being fully viable and operational at room temperature.

Intel continues to introduce new concepts in physics with breakthroughs in delivering better qubits for quantum computing. Intel researchers are working to find better ways to store quantum information by gathering a better understanding of various interface defects that could act as environmental disturbances affecting quantum data.

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